1. Field
This disclosure relates generally to the design, implementation and utilization of electronic circuits, and more specifically, to methods for processing an electronic circuit design and placing vias within an electronic circuit design and an electronic circuit produced utilizing such a method(s).
2. Related Art
As linewidths and feature sizes have decreased and interconnect density has increased, a phenomenon known as “stress migration” (also known as “stress-induced voiding” or “cavitation”) has become more prevalent. Stress migration causes voids in metallization interconnect lines which degrade electronic circuit performance, eventually leading to open circuit conditions and electronic circuit or device failure. The problem of stress migration is typically attributable to the differing rates of thermal expansion existing between interconnect materials, substrate materials, and inter-level dielectric (ILD) materials and vacancy migration driven by the hydrostatic stress gradient. The thermal expansion coefficients of conducting materials (e.g., aluminum, copper, and the like) may be many times as great as the thermal expansion coefficients of substrate (e.g., silicon) and ILD materials which encase them, particularly low-κ and ultra low-κ ILD materials. Consequently, conducting or “metallization” material expands and contracts at a different rate than surrounding semiconductor and dielectric materials during heating and cooling cycles of semiconductor fabrication processes or electronic circuit use. The vacancies tend to migrate to and collect at vias, thereby leading to void formation, which over time can grow and lead to an open connection, thus leading to circuit failures. The inclusion of redundant vias is one effective method to reduce yield loss related to stress-migration-related failures, but a large number of extremely complex design rules make redundant via insertion a complex and difficult task. There is therefore a need to more accurately determine where to place redundant vias within electronic circuit designs.
FIGS. 2 and 3 illustrate a table of conventional fixed threshold distance-spacing design rules for a via metallization feature independently utilizing interconnect metallization feature height and width ranges and a graphical representation of categories of fixed threshold distances defined using such design rules according to the prior art.